1. Field of the Invention
The present invention relates generally to methods for forming epitaxial layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming, with attenuated defects, epitaxial layers within microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices and over which are formed patterned conductor layers which are separated by dielectric layers.
As is common in the art of semiconductor integrated circuit microelectronic fabrication, semiconductor devices when formed within and upon semiconductor substrates are typically and preferably formed within and upon epitaxial semiconductor layers (typically epitaxial silicon semiconductor layers) which are formed upon bulk semiconductor substrates (typically bulk silicon semiconductor substrates). Epitaxial semiconductor layers are desirable in the art of semiconductor integrated circuit microelectronic fabrication insofar as epitaxial semiconductor layers may often mask structural defects within bulk semiconductor substrates upon which they are formed.
While epitaxial semiconductor layers are thus clearly desirable in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, epitaxial semiconductor layers are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, while epitaxial semiconductor layers may often mask structural defects within bulk semiconductor substrates upon which they are formed, epitaxial semiconductor layers are not always themselves readily formed absent defects within the art of semiconductor integrated circuit microelectronic fabrication.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide methods and materials for forming within semiconductor integrated circuit microelectronic fabrications epitaxial semiconductor layers with attenuated defects.
It is towards the foregoing object that the present invention is directed.
Various methods and apparatus have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with desirable properties, epitaxial semiconductor layers upon bulk semiconductor substrates employed for forming the semiconductor integrated circuit microelectronic fabrications.
Included among the methods and apparatus, but not limited among the methods and apparatus are methods and apparatus disclosed within: (1) Ruehrwein, in U.S. Pat. No. 4,062,706 (a chemical vapor deposition (CVD) method for forming epitaxial III-V semiconductor layers upon semiconductor substrates absent a hydrogen carrier gas within a chemical vapor deposition (CVD) reactant gas composition, by employing as the chemical vapor deposition (CVD) reactant gas composition: (a) a first reactant gas comprising an inert carrier gas, a hydrogen halide and a group III element gas or vapor; and (b) a second reactant gas comprising an inert carrier gas with a volatile group V compound or a group V element gas or vapor); and (2) Katz et al., in U.S. Pat. No. 4,113,547 (a chemical vapor deposition (CVD) method for forming, with enhanced across substrate uniformity, epitaxial silicon semiconductor layers upon silicon semiconductor substrates employed within silicon semiconductor integrated circuit microelectronic fabrications, by enclosing with a thermally insulative ring within an epitaxial silicon semiconductor layer deposition apparatus a peripheral rim section of a silicon semiconductor substrate prior to forming thereupon an epitaxial silicon semiconductor layer).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials which may be employed for forming, with attenuated defects, epitaxial semiconductor layers within semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming an epitaxial semiconductor layer within a semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the epitaxial semiconductor layer is formed with attenuated defects.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming an epitaxial semiconductor layer within a semiconductor integrated circuit microelectronic fabrication.
To practice the method of the present invention, there is first provided a monocrystalline substrate. There is then formed over the monocrystalline substrate an epitaxial semiconductor layer while employing a plasma enhanced chemical vapor deposition (PECVD) method. Within the present invention, the epitaxial semiconductor layer comprises at least one of silicon and germanium. Similarly, within the present invention, the plasma enhanced chemical vapor deposition (PECVD) method employs a reactant gas composition comprising: (a) at least one of a silicon source material and a germanium source material; and (b) an inert carrier gas.
The present invention provides a method for forming an epitaxial semiconductor layer within a semiconductor integrated circuit microelectronic fabrication, wherein the epitaxial semiconductor layer is formed with attenuated defects.
The present invention realizes the foregoing object by employing within a plasma enhanced chemical vapor deposition (PECVD) method for forming an epitaxial semiconductor layer upon a monocrystalline substrate, where the epitaxial semiconductor layer comprises at least one of silicon and germanium, a reactant gas composition comprising: (1) at least one of a silicon source material and a germanium source material; and (2) an inert carrier gas.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally conventional in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of specific process limitations to provide the method of the present invention. Since it is thus at least in part a series of specific process limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.